MATLAB: No of Pipeline Stages in Verilog coming from an m file (or latency)

HDL Coder

How does one find how many pipeline stages exist in the verilog file. Example, run the mdhlc_sobel filter example from the web site and just pushing the default buttons in work flow advisor I get the design to run fast exceeding my system requirements. However, I dont know how many pipeline registers were put in there. The verilog code seems to show 12 – 15 or more stages (not sure) but I cannot tell what the latency will be. Also, it is hard to see the structure/data flow in the verilog code due to the number of times variables change names and then are pipelined. Version is 2014a.

Best Answer

The short answer is that the conversion of the original untimed MATLAB code to sequential HDL requires multiple clock cycles to implement. This is just part of the nature of the algorithm, so will vary depending upon the particular design. I'm not familiar with this particular example so I can't say what causes the code to require conversion to sequential form like this.

For your question #1: HDL Coder is indicating that the generated HDL contains a latency of n cycles. With no explicit pipelining, the conversion of the algorithm from untimed MATLAB code to sequential HDL code requires n cycles to complete in HDL. You do not need to add explicit pipelining unless desired. The delays are not pipeline registers per se, but are required for the algorithmic conversion.

Question #2 is a more generalized FPGA design question. The 'correct' answer may depend upon your algorithm, your target device, synthesis tool, whether HDL Coder is using Distributed Pipelining, and many other factors. I don't think that there is a hard and fast answer to this other than "whatever works well for your design environment".

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This is typical behavior when generating VHDL code for a subsystem. By default, the generated model inserts delays in the model to account for hardware implementation on an FPGA. Notice the output in the Command Window upon generating code from such a subsystem:

### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 23 cycles.

When the HDL code is implemented in hardware, we cannot expect correctly computed values until after a certain amount of time steps. In the attached example, notice that increasing the simulation time to 50 seconds and then generating HDL code will result in a generated model that will show the expected output after 23 cycles have elapsed.

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