MATLAB: HDL Coder Pipeline Sample Rate

Question

I am using HDL Coder for controller implementation. My controller desired sample rate is far below that of the device it will run on. What is the cleanest way to insert pipeline registers havins sample rate of base device clock, as opposed to the controller base rate?

Thanks

Answer 1

Hi Jeff, very good question. What release of HDL Coder are you using?

This is a known issue and we are providing new capability in the latest release, 14b, which will come out in October this year. The new capability is called "Clock Rate Pipelining" and in this mode, the coder understands this sampling difference. When you then insert an input/output pipeline between your filter sections, it will insert it at the FPGA clock rate.

Unfortunately, for now with your current HDL Coder version, you will have to model your design at the FPGA clock rate to achieve the same behavior. I understand that this will slow down your simulation but it is the only way right now.