MATLAB: Insert algorithms on Verilog language to Simulink
simulinkverilog
How to insert algorithms on Verilog language to Simulink?
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If you have HDL Verifier, you can cosimulate your design with Simulink using either Cadence Incisive or Mentor Graphics ModelSim. You will of course need one or the other of the HDL simulators.
The high-level overview is that you create a HDL cosimulation block in Simulink that has the same interface as your top-level Verilog code. Simulink then executes its simulation, calling the HDL simulator each time the cosimulation block is scheduled to execute.
EDA Simulator Link™ currently supports both Mentor Graphics® ModelSim® and Cadence® Incisive® mixed-language HDL simulators for HDL cosimulation with Simulink®. Some previous releases also supported cosimulation with Synopsys® simulation tools as well.
MATLAB itself cannot be used for HDL simulation - you will need software like Modelsim or Synopsys to do this. However, usingEDA Simulator Link, you can generate a testbench in MATLAB and send it to an HDL Simulator to verify your HDL code.
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