I have a simple funtion to test the HDL Coder.
It is as follows:
function [sumnumn, diffnum, prodnum, quotnum] = asmd2num(a, b)
sumnum = a + b;
diffnum = a – b;
prodnum = a * b;
quotnum = a / b;
end
For the Clocks & Ports tab I have Synchronous,
Inpud data type = signed/unsigned
Output data type = signed/unsigned
Optimzations: Register Outputs
The issue is that the HDL output is always producing unsigned outputs.
How does one get SIGNED outputs?
And preferably SIGNED inputs?
Thanks
Best Answer