MATLAB: HDL Coder disable Clock Enable output port

Question

How can I disable the Clock Enable output port in generated VDHL-Code?

I can specify the name In HDL Code Generation -> Global Settings -> Ports -> Clock enable output port (default ce_out). But there is no checkbox to disable the output port.

The documentation says "A clock enable output is generated when the design requires one."

What is the condition for "when the design requires one"?

Answer 1

There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on the output.