I cannot find HDL operations -> Blocks -> simple dual port RAM. I use Matlab 2011b.
Also, is there a Xilinx RAM block for system generator (14.2) that has read address and read enable port? because the existing dual port RAM in system generator has only write enable and write address ports.
In both of the above issues, will upgrading to MATLAB 2014a and xilinx 14.7 will solve the problem for sure? I ask this because, in the Xilinx System Generator 14.2 guide, there is a mention about the Simple Dual port RAM and True Dual port RAM.
Dear community members, any help will be appreciated. Thank you.
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