Hi,
Is there anyway to generate HDL code for a reference model . For example, let's say I have a subsystem that I would like to use across my design. There are currently two problems with repeating the same subsystem across the model. One is that the generated code outputs different Verilog files for each of the called subsystem. Second is that if I want to make a change to the subsystem, the change will not happen across the other subsystems. Is there a way to create a subsystem, that can be modified globally and at the same time generate only one Verilog file?
Many thanks, Kamyar
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