Hello Mathworks-Community,
I’m trying to generate VHDL code with Matlab 2016a. Using sharing, Clock-Rate-Pipelining and delays in atomic subsystems. However, these options seem to exclude each other somehow.
I have attached the model I’m trying to generate.
Problem: I have modeled a closed-loop control system for avionic systems. Output/Path-Delays are therefore unacceptable. The included atomic subsystems (reduced to the troublemaking delay block) shall be shared and pipelined. Pipelining obviously introduces latencies/path-delays. To find a solution to this problem, I read the Clock-Rate-Pipelining article in the documentation: http://www.mathworks.com/examples/simulink-hdl-coder/mw/hdlcoder_product-hdlcoder_clock_rate_pipelining-clock-rate-pipelining CRP pipelines the clock-path, not the data-path. This is what I want. However, the HDL coder seems to completely fail to share subsystems and pipeline them in the clock-path, when the subsystem contains delay blocks. I’ve tried different combination of flags (Distributed Pipelining, Balance Delays, Oversampling factor, etc.), but no configuration seemed to generate the desired model. When I remove the delay from the subsystems, HDL coder generates the desired model and code.
Is this a bug, is the configuration incorrect, or simply not supported by the HDL coder?
Greetings from Germany Hagen Hasberg
PS: readme.txt contains some additional information about the problem.
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