MATLAB: Simulink HDL Coder – Filter – Fully Serial Interfacing

Question

I have generated an IIR filter using FDAtool, ported it to simulink, and got it running on an FPGA in full parallel mode. Now I want to implement the fully serial architecture, but I cannot find an example timing diagram for interfacing with the top level entity of the filter. Does anyone know where to find such an example timing diagram which explains how to interface with the fully serial filter?

Thanks

Answer 1

There is no timing diagram readily available, but if you look at the HDL code, you will see the interface is to provide a clock input that is N times faster (the setting for N is displayed during HDL code generation: Clock Rate is N times the sample rate for this architecture) and feed in the data/samples at 1/N the clock rate.

You can also generate a testbench for the design, which will show how to do this in HDL.