MATLAB: Is the generated HDL Code having a faster clock rate than the designed Simulink model

Question

My Simulink model executes at a fixed-step size of 100ns (1e-7 s). Subsystems and reference models inside this model also execute at 100ns or do have conditional execution. But in the generated HDL code, external clock is every 100 ns, but the reference models are enabled every 4.9 us. Why is this?

Answer 1

In this case HDL Coder has found the need to overclock the design due to the presence of filters in the subsystems whose architectures are all "Fully serial". From the documentation for the filter, we can see that:

"In a fully serial architecture, the system clock runs at a much higher rate than the sample rate of the filter. Thus, for a given filter design, the maximum speed achievable by a fully serial architecture is less than that of a parallel architecture."

Hence, a different architecture will result in a different overclocking requirement.

Documentation:

https://www.mathworks.com/help/hdlcoder/ug/configuring-hdl-filter-architectures.html