Hi, i want to design simple filter using discrete TF block TF=(1/(1+ 0.1z^-1 + 0.1z^-2)) and writing its VHDL code to be synthesized in cadence. i checked with input of const block=2 with default data type inherited and ufixdt(1,16), it works well.
but i dont know when it is synthsized in cadence will it provide me input port where 4bit ADC can be connected (ADC is driveing block). my target input to the discrete filter block which accepts 4bit signal from ADC. how can a 4bit filter be designed. does the input constant block data type in simulink affects the synthesized code. e.g in simulink run, scope give same result either inherited … or ufixdt(1,16) ? thanks
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