To practice with the HDL coder, I translated a M function into a VHDL one, and noted two additional arguments in the resulting VHDL function: clk and clk_ena.
I (wrongly) assumed that to have control on those parameters I had to use exactly those two parameter names in the original M function, but once again the translation caused two extra input parameters to be added to the VHDL function, although with different different names (like clk2 or so).
How can I have direct control of the clock? And what if I don't want to use a clock enable? Do I have to remove them from the VHDL code once generated? This would be bad in case of large code.
Thanks Alberto
Best Answer