MATLAB: Is it possible to control the data type of GENERIC parameters in VHDL generated by HDL Coder

Question

I would like to control the data type of GENERIC parameters in VHDL generated by HDL Coder.  I have a subsystem mask parameter for the Top-level system (DUT) for which I am generating code.  I would like this mask parameter to appear as 'std_logic_vector' in the generated code.  Is it possible to define this data type for a subsystem mask parameter of the top level subsystem?  (R2017a)

Answer 1

It is only possible to define the generated data type of a subsystem mask parameter in limited cases.  There is an interface generation parameter, 'GenericList', which is used for this purpose.  However, as I mentioned there are limitations on when the 'GenericList' name-value pair is available for a block.  For instance, this option will be available for a subsystem with a black box implementation.  See following documentation more about the 'GenericList' option and how it is used:

https://www.mathworks.com/help/releases/R2017a/hdlcoder/ug/customizing-the-generated-interface.html?

In this case, setting the subsystem as a Black Box Interface would not be possible because this setting is only available for subsystems below the level of the DUT.  

See the following documentation for more information on what a Black Box Interface is:

https://www.mathworks.com/help/releases/R2017a/hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html?