MATLAB: Is FTDI USB-JTAG supported for FPGA-in-the-Loop (FIL) simulation

HDL Verifier

I have a model such as the example model "fil_pid.slx". I go through HDL Workflow Advisor for this model to load it to my FPGA board. All of the steps are passed and the model is successfully loaded to the board. When I try to run the model in FIL however, I get the following error:
Did not find any Digilent® JTAG cable. Make sure that the cable is connected to your computer.
Failed to initialize the RTIOStream library.
My board uses an FTDI chip for its USB-JTAG connection. I have checked my JTAG connection and I am able to see the I am connected to the board. I am able to successfully load programs through this connection.

Best Answer

As of MATLAB R2019a, only MATLAB as AXI Master and FPGA Data Capture applications are supported with a FTDI USB-JTAG connection, while FIL simulations are not. This will cause the error seen above. See the link below for JTAG requirements for FPGA-in-the-Loop:
https://uk.mathworks.com/help/releases/R2019a/hdlcoder/ug/what-is-fpga-board-customization.html#bt72ftg-1
For board using a Digilent chip, MATLAB as AXI Master, FPGA Data Capture, and FIL applications are all supported. For board with a standard Xilinx 14 pin JTAG connector, use an HS2 or HS3 cable from Digilent and use that for JTAG FIL simulations:
https://store.digilentinc.com/jtag-hs3-programming-cable/
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