MATLAB: How to write hdl testbench inside matlab using system clock delays for simulink hdl model verification

Question

Hi, can I write testbench for verilog/vhdl based simulink blackbox model, without exporting to HDL (xilinx-ISE/modelsim) simulator.

One big doubt is that, I am writing a mcode block sung simulink. When I write test vectors using matlab function, can I add a system delay, like advancing the clock for few time samples(with the current inputs as it is). While writing testbench in HDL files, this option is there, like in verilog we say " #10 ns; " and the system clock advances 10ns. How do we do this in matlab.

Answer 1

I think what you are asking is, can you use a Simulink model to provide the stimulus to HDL code while the HDL simulates inside a 3rd party HDL simulator. if this is what you are asking, the answer is 'yes'. Simulink<-->HDL simulator cosimulation is provided by the HDL Verifier product.

HDL Verifier will take the Simulink data at the inputs of the cosimulation block and transmit it to the the HDL simulator (ModelSim or Cadence Incisive). It will then execute the HDL simulation for one clock cycle, and send the results generated on the HDL output ports back to Simulink. These results then propagate throughout the rest of the Simulink model like any other signals.

If you want to provide any specific time-based waveform to the HDL via the cosimulation block, you just need to generate that waveform in Simulink on the signals leading to the cosimulation block inputs.