MATLAB: How to apply constraints on test signals being generated by Design Verifier

Simulink Design Verifier

I am trying to generate test cases for increased model coverage of a model, using design verifier. The problem is that some test cases generated by Design verifier have impractical negative values for signals that cannot be negative in reality. Is there a way to apply any constraints to test cases generated by Design Verifier?

Best Answer

Hi Tushar,
The signals in the test cases can be constrained by using ‘Test Condition’ block from Simulink Design Verifier library. The following demo will be more helpful in understanding the functionality of this block.
sldvdemo_debounce_testconblk
The additional information of this block is available on the documentation page:
https://www.mathworks.com/help/sldv/ref/testcondition.html?s_tid=doc_ta
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