Hi, I'm trying to generate HDL code for a simple flip flop that will pass HDL synthesis.
I have tried the suggested solution of using a unit delay block, but this is unacceptable because the unit delay block uses reals (incompatible with the HDL synthesis process)
I am currently receiving the error: "Output port 'Q' must have 'Output when disabled' set to 'held' for HDL code generation" when I use the D-flip-flop block in the "Simulink Extras" section.
I understand the error, but I don't understand how I can implement the fix.
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