Hi,
I am working on a project implementing 16 QAM transmitter on a FPGA.I started by developing a simulink model followed by HDL code generation by HDL coder . My cosimulation of developed code with Model Sim works as per desired but when the same code was implemented in FPGA with same clock settings,the working was not as desired.I got an unsatisfactory constellation output. Someone please suggest me the reasons for such an occurence.
Krishnakumar
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