Hello,
I would like to implement an FFT on my FPGA. On my FPGA I receive data continuously with a specific clock one sample after another. I would like to buffer 64 samples and then perform the FFT on those.
The Simulink model that describes the idea (but is not HDL compatible) looks simple:
I created the following example using the HDL optimized FFT and a Buffer outside the Subsystem.
This creates a top level HDL file that uses as an input to the FFT Subsystem an array of std_logic_vectors:
In1 : IN vector_of_std_logic_vector16(0 TO 63); -- ufix16_En8 [64] ... TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(15 DOWNTO 0);I am know looking for ways to create this buffer that is currently only working in simulink in hardware. Preferably using simple block RAM. Sofar I found the line_buffer (in the eml_hdl_design_patterns library) and the HDL FIFO. But with both I seem to not achieve my goal.
I am happy about any kind of hinds or reference examples. So far my search hasn't revealed anything and I am a little lost how to create a HDL compatible Buffer. Or how else to use the FFT?
Best Answer