MATLAB: Can I define customized Bus Data Types as input data types to HDL Coder DUT

HDL Coder

Can I define customized Bus Data Types as input to HDL Coder DUT?

We normally define control registers which are bit fields (start bit, operation mode on 3-bits…). I tried to mimic this by defining a bus (Control_Bus) representing the control register structure. Unfortunately, I could not select AXI-4 Lite for the input with type Control_Bus.

Best Answer

As of MATLAB R2018b, the HDL Coder's implementation of the AXI4 slave interface does not support bus data types. The workaround is to use the bitslice/bitconcat block on a uint input signal and slice it according to your custom data type. You will want to fully document your constructed data type and define what each bit position signifies.

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MATLAB: How to create a FFT ipcore for Zynq using Simulink HDL Coder

A frame-based block takes an entire array of data as an input in one time step. This is not very hardware friendly; for hardware, you need to stream your data in one array element at a time. HDL Coder has a "HDL Streaming FFT" block and a "HDL FFT" block designed specifically for hardware implementation. You will need to modify your design to interface with one of these blocks. To access this block in R2013a:

 >> hdllib

This library contains all blocks that support HDL code generation.

Double-click on "HDL Demo Library".
Choose the "HDL Streaming FFT" or "HDL FFT" block.

A more direct route to the block is to open the HDL Demo Library directly:

 >> hdldemolib

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

As of MATLAB R2019a, HDL Coder only supports one Slave (input) AXI4-Stream interface, and one Master (output) AXI4-Stream interface per IP core. For many SDR and video applications, multiple input or output channels are needed.

At this time, a possible workaround is as follows:

1) In HDL Workflow Advisor Task 1.1, it is necessary to select a specific board for "Target platform" (e.g. "Zedboard"). If you select "Generic Xilinx Platform", it is not currently possible to support this workflow

2) Create and register a custom reference design for the selected board, following the workflow outlined here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/ug/register-a-custom-reference-design.html

To ease this process, you can refer to an existing reference design for the selected board. For example, on a Windows machine the AXI4-Stream reference design for the Zedboard could be found at:

 C:\ProgramData\MATLAB\SupportPackages\R2019a\toolbox\hdlcoder\supportpackages\zynq7000\+ZedBoard\+vivado_stream_2018_2

This will also require exporting a block design from Vivado. A full example of this workflow can be found here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html#d117e22885

3) In the custom reference design file (e.g. "plugin_rd.m"), call the "addAXI4StreamInterface" function multiple times to define multiple AXI4-Stream interfaces. Each one of these can be specified with a different Interface ID to distinguish them. For example, you might do the following in your custom reference design file:

% add first AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_1');
% add second AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm_2/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s_2/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_2');

4) Once this custom reference design is created, you can select it in HDL Workflow Advisor Task 1.2.

5) In HDL Workflow Advisor Task 1.3, you can now select from multiple AXI4-Stream interfaces. Note that due to the current limitations, it will be necessary to model and map the READY signals for all the AXI4-Stream interfaces.

Best Answer

Related Solutions

MATLAB: How to create a FFT ipcore for Zynq using Simulink HDL Coder

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

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