[Tex/LaTex] Insert code or text file in latex as is

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Question : How can I insert a txt file ( a source code) as such in latex without any change in indentation, tabs, formatting etc?

Scenario :

Consider I have a text file as below ( It is a part of a VHDL code edited in gEdit ):

enter image description here

I want to include this code in Latex as it is.

I used verbatim method available in Kile, and below is the result I got :

enter image description here

You can see the tabs and indentation is dislocated. ( This is just a small part, remaining part is also similar, means, everything dislocated)

How can I add this code as such into a latex file ?

EDIT :

I also used listings package. Again the same problem. Intendation is not correct. Also, it even cut some portions of text on the right side. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP_MODULE is
    port (CLK          : IN STD_LOGIC;                   -- clock
          RESET        : IN STD_LOGIC;                   -- reset signal
          DECODED_DATA : OUT STD_LOGIC_VECTOR(0 TO 15)   -- decoded message
          );
end TOP_MODULE;

Best Answer

You probably have tabs in your input file. You can, however, fix it without changing your input file, with either fancyvrb or listings; both packages allow also for making the type size smaller, so that the code fits in the margin.

\documentclass{article}
\usepackage{fancyvrb} % for simple solution
\usepackage{listings,color} % for colored solution

% for colored solution
\lstnewenvironment{VHDLlisting}[1][]
  {\lstset{
    language=VHDL,
    basicstyle=\footnotesize\ttfamily,
    columns=flexible,
    keepspaces=true,
    keywordstyle=\color{red},
    identifierstyle=\color{green},
    commentstyle=\color{blue},
  }}{}

\begin{document}

% simple solution (no colors)

\begin{Verbatim}[tabsize=8,fontsize=\footnotesize]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP_MODULE is
    port (CLK          : IN STD_LOGIC;                   -- clock
          RESET        : IN STD_LOGIC;                   -- reset signal
          DECODED_DATA : OUT STD_LOGIC_VECTOR(0 TO 15)   -- decoded message
      );
end TOP_MODULE;
\end{Verbatim}

% colored solution

\begin{VHDLlisting}[tabsize=8]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP_MODULE is
    port (CLK          : IN STD_LOGIC;                   -- clock
          RESET        : IN STD_LOGIC;                   -- reset signal
          DECODED_DATA : OUT STD_LOGIC_VECTOR(0 TO 15)   -- decoded message
      );
end TOP_MODULE;
\end{VHDLlisting}

\end{document}

In the example, the line that shows only ); has a tabulation character in it, just to show that the packages can cope with it. It's, to be precise,

<TAB><SP><SP>);

so that in my editor, where tabs cover 8 spaces, it is right for aligning the parentheses under the "D" in the line above it.

However, changing tabs into spaces is better: editors have different ideas about how long is a <TAB>, so what aligns in an editor may appear misaligned in another.

enter image description here

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