HDL Coder supports Xilinx Vivado Design Suite since R2014b. Here is a list of MATLAB releases and the respective Xilinx Vivado versions that HDL Workflow Advisor has been tested against:
- R2021a: Xilinx Vivado 2020.1
- R2020b: Xilinx Vivado 2019.2
- R2020a: Xilinx Vivado 2019.1
- R2019b: Xilinx Vivado 2018.3
- R2019a: Xilinx Vivado 2018.2
- R2018b: Xilinx Vivado 2017.4
- R2018a: Xilinx Vivado 2017.2
- R2017b: Xilinx Vivado 2016.4
- R2017a: Xilinx Vivado 2016.2
- R2016b: Xilinx Vivado 2015.4
- R2016a: Xilinx Vivado 2015.2
- R2015b: Xilinx Vivado 2014.4
- R2015a: Xilinx Vivado 2014.2
- R2014b: Xilinx Vivado 2013.4
Notes:
(1) For the Generic ASIC/FPGA workflow in HDL Workflow Advisor, note that the above list states the last supported Xilinx Vivado version for each release. For example, if you work with HDL Coder R2020a, you will be able to use HDL Workflow Advisor with Xilinx Vivado 2019.1 and all previously tested Xilinx Vivado versions, all the way back to 2013.4.
(2) For the IP Core Generation workflow in HDL Workflow Advisor, you will often need to use the exact Xilinx Vivado version that is stated in the list above for your release, or one of the exact version(s) that is supported by the reference design that you are using. You can see this information in HDL Workflow Advisor step 1.2. after selecting your desired reference design.
For more information regarding synthesis tool and device support by HDL Coder, see the "Supported Third-Party Tools and Hardware" documentation page for your respective MATLAB release:
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