I use Xilinx Blockset/Basic Elements/Black Box to integrate my hand-writing VHDL code under my "Top" subsystem block, and then I want to use HDL Workflow Advisor to generate my FPGA block. I got the error message.
Error reported by S-function 'sysgen' in 'blackbox_fpga/Top/Black Box': An internal error occurred in the Xilinx Blockset Library.
Thanks in advance for any help.
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