MATLAB: Does synthesis fail for ZC706 or other high-cost boards when using free Vivado WebPACK edition

failedfilesgenerationHDL CoderHDL Verifierprogrammingvivadowebpackzc706

So far, we have successfully used low-cost boards such as Zedboard and Xilinx ZC702 with HDL Coder and HDL Verifier. The integrated synthesis and download workflows offered by the "HDL Coder/HDL Verifier Support Packages for Xilinx FPGA boards" ran smoothly.
With our newly purchased Xilinx ZC706 board, the synthesis does not seem to work anymore.
For example, when we tried to run the "Verify Setup" test during the "HDL Verifier Support Package for Xilinx FPGA boards" hardware setup, the programming file generation failed. Below error can be observed at the MATLAB command line and in the "fil_test_fil.log" file:
# open_run impl_1 
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open

Best Answer

This error may be due to a Vivado licensing error. This can be confirmed by opening the Vivado Project File (.XPR) in Vivado IDE, which will reveal the following error on the "Messages" tab:
[Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining which features and devices are licensed for your system.
For example, the no-cost Vivado WebPACK edition only supports a limited set of commercial devices. See the following Xilinx documentation page for a list of all FPGA devices supported by WebPACK:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture
While Vivado WebPACK supports the low-cost XC7Z020 device used on Zedboard and Xilinx ZC702, an additional license is required for the synthesis of the XC7Z045 Zynq device used on Xilinx ZC706.
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