MATLAB: Does setting of the ‘samples per frame’ value to high number and selecting a low ‘sampling rate’ in dm6437evm ADC/DAC blocks create a delay in generated code in Target Support Package 4.0 (R2009b)

Target Support Package

The ADC block takes input from the Lin In and the DAC block outputs on Lin Out. When the Sampling frequency selected is 8 KHz and the number of samples per frame is 8192, a delay of ~3 seconds is observed between the input and the output of the model.
However, when the sampling frequency is changed to 96 KHz (highest available) then the delay is not observable. Also, if the samples per frame are set to be 64 (keeping the frequency at 10 KHz) the delay is not observable.

Best Answer

The number of samples per frame parameter in the ADC block controls how many samples are queued internally in the device buffer before the device buffer is handed out to the caller. The ADC driver has to wait until it queues all samples otherwise data handed out to the caller will be corrupt.
For 8 KHz, ADC output would be delayed by 8192/8e3 ~ 1 seconds. Same applies to the DAC block. So the minimum digital delay for a loopback application is 2 frames, 2*8192 samples, which correspond to approximately 2 seconds.
Now this is just the digital delay, there is also analog delay in the driver path due to signals traveling from AIC33 codec to Multichannel Buffered Serial Port Multi Channel Buffered Serial Port (McBSP) and vice versa. All of these delays, when added up explain why the output is delayed relative to input.
The way to minimize the delay is to either increase the sampling rate or decrease the number of samples per frame.