MATLAB: Where can I get information on the Synplify DSP HDL Generator for Simulink

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Where can I get information on the Synplify DSP HDL Generator for Simulink?

Best Answer

The Synplify DSP HDL Generator from Synplicity generates HDL code for DSP / FPGA hardware from Simulink models. Synplify DSP consists of a proprietary Blockset and an HDL generator for those blocks. It does not generate HDL for standard Simulink or MathWorks Blockset blocks.

Synplify DSP supports Simulink floating and fixed point datatypes. Required products are MATLAB, Simulink, and the Fixed Point Blockset.

MathWorks does not provide support for the Synplify DSP HDL Generator. If you have questions regarding Synplify DSP for Simulink, you should contact the Synplicity support group.

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MATLAB: Dsp

xcorr() with the 'coeff' option.

x = randn(1000,1);
y = randn(1000,1);
[C,lags] = xcorr(x,y,20,'coeff');

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

Hi Yashar,

Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.

IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html

http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle

You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html

FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards

http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html

Thanks, Wang

Best Answer

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MATLAB: Dsp

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

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