I need to use an IP core generated with HDL Coder in Xilinx Vivado 2014.2. The core generated by the coder is intended to be used in Xilinx EDK. The IP core converter implemented in Vivado 2014.2 has troubles to identify the AXI interfaces in my core correctly, so I would have to set the AXI parameters manually, which is a very time consuming task, especially if performed more than once. Will you support direct generation of IP cores for Vivado in the future?
MATLAB: Using HDL Coder IP core in Xilinx Vivado instead of EDK
HDL Coderip core generationvivado
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