MATLAB: Unable to see AXI Video stream in/out on HDL Advisor for the Sobel filter reference design.

axi streamHDL Codersimulinkvideo streamzedboardzybozynq

 Unable to see AXI Video stream in/out on HDL Advisor for the Sobel filter reference design. I have updated the hardware support packages. My target is either Zybo or Zedboard. I also tried choosing Generic. I have followed all the steps in the http://in.mathworks.com/help/hdlcoder/examples/using-ip-core-generation-workflow-sobel-edge-detection.html

Best Answer

Hi, are you using Xilinx ISE as synthesis tool? In R2016a or earlier version, the "AXI4-Stream Video" interface is only support in Xilinx ISE IP core.

If you are using Xilinx Vivado, you could optionally use "AXI4-Stream" interface to transfer your video signal.

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

As of MATLAB R2019a, HDL Coder only supports one Slave (input) AXI4-Stream interface, and one Master (output) AXI4-Stream interface per IP core. For many SDR and video applications, multiple input or output channels are needed.

At this time, a possible workaround is as follows:

1) In HDL Workflow Advisor Task 1.1, it is necessary to select a specific board for "Target platform" (e.g. "Zedboard"). If you select "Generic Xilinx Platform", it is not currently possible to support this workflow

2) Create and register a custom reference design for the selected board, following the workflow outlined here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/ug/register-a-custom-reference-design.html

To ease this process, you can refer to an existing reference design for the selected board. For example, on a Windows machine the AXI4-Stream reference design for the Zedboard could be found at:

 C:\ProgramData\MATLAB\SupportPackages\R2019a\toolbox\hdlcoder\supportpackages\zynq7000\+ZedBoard\+vivado_stream_2018_2

This will also require exporting a block design from Vivado. A full example of this workflow can be found here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html#d117e22885

3) In the custom reference design file (e.g. "plugin_rd.m"), call the "addAXI4StreamInterface" function multiple times to define multiple AXI4-Stream interfaces. Each one of these can be specified with a different Interface ID to distinguish them. For example, you might do the following in your custom reference design file:

% add first AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_1');
% add second AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm_2/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s_2/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_2');

4) Once this custom reference design is created, you can select it in HDL Workflow Advisor Task 1.2.

5) In HDL Workflow Advisor Task 1.3, you can now select from multiple AXI4-Stream interfaces. Note that due to the current limitations, it will be necessary to model and map the READY signals for all the AXI4-Stream interfaces.

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

Hi Yashar,

Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.

IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html

http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle

You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html

FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards

http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html

Thanks, Wang

Best Answer

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

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