MATLAB: Tool boxes required to generate IP CORE from SIMULINK

HDL Codersimulinktoolboxes required

Hello,

I saw an video (Create simple "Add" Block, and generate RTL by HDL Coder in Simulink [HDL coder + Zynq Project]) which clearly shows that we can generate IP CORE from Simulink. Apart from the products MATLAB and Simulink, what are the other toolboxes that are required to generate an IP CORE using this workflow (to port on Zynq FPGA)?

Thanks

Pankaja

Best Answer

HDL code and IPCore generation are provided by HDL Coder. HDL Coder has as required products MATLAB, Fixed-Point Designer and MATLAB Coder.

For documentation of the HDL Coder required products list see mathworks.com.

Related Solutions

MATLAB: Is it possible to integrate Semiconductor Intellectual Property core (IP core) into a Simulink model using Simulink HDL Coder 1.6 (R2009b)

The ability to integrate Semiconductor Intellectual Property core (IP core) into a Simulink model is available in Simulink HDL Coder 1.6 (R2009b).

If the IP core is in VHDL/Verilog, the Black box custom code integration can be used. It allows user to integrate their own IP in the code generated from Simulink HDL Coder. User must simply choose 'Black box' as the implementation of a subsystem through the control file. For more information on custom code integration through black box, refer to the documentation link below.

 <http://www.mathworks.com/help/hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html>

Another approach could be to use the EDA Simulator Links product. It allows user to co-simulate the IP core using a third party VHDL/Verilog simulator with MATLAB and Simulink.

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

Hi Yashar,

Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.

IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html

http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle

You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html

FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards

http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html

Thanks, Wang

Best Answer

Related Solutions

MATLAB: Is it possible to integrate Semiconductor Intellectual Property core (IP core) into a Simulink model using Simulink HDL Coder 1.6 (R2009b)

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

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