This is a question related to 19.2.1 version of:
Communications Toolbox Support Package for USRP Embedded Series Radio
Communications System Toolbox Support Package for Xilinx Zynq-Based Radio
Embedded Coder Support Package for Xilinx Zynq-7000 Platform
Where ADI's libiio drivers replace MW proprietary drivers, in particular for DMA/ AXI-stream communication through the Programmable Logic/FPGA.
From documentation it seems likely that the ADI libiio takes over all interfacing between SW on the Linux/ARM and both FPGA IP's, the ADI RF chip and also other peripherals.
Is this the case or is there more to it?
In the reference FPGA design for libiio distributed with "Communications Toolbox Support Package for USRP Embedded Series Radio", we can still see MW IP's (mainly some clock net manipulation and bypass muxing of user IP) if we look in the generated Vivado project.
Does this mean that there exists corresponding (to the PL/FPGA reference design) SW or kernel components made by MW necessary for a running SW/FPGA system on the Zynq?
So that the only Linux image that will work with the MW reference top level design is the corresponding image from the Support Package?
Can you please provide some structural/version details?
Also:
When moving to 2019b and libiio, can we expect all functionality available for a user SW application running on target (MW SD card from support package) to be as described on ADI's iio webpages, for example
Or are there conditions/restrictions?
Best regards,
Terje
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