MATLAB: Signal measurement error when using “download”-option in HDL Workflow Advisor

Question

Hello, I have recently begun using the Zedboard with the HDL Coder Toolbox and it have worked quite well so far. However, I have now been trying to resolve an error for quite a while that is related to running a .bit-file using the XADC-interface from the Zedboard's SD-card.

What happens is that if I use Xilinx' XADC-interface in my reference design, it will produce wrong measurements after around 5 seconds of running. Important to note is that this only happens if I use the "Download" option in step 4.4 in the HDL Workflow Advisor. If I program the Zedboard through either the JTAG-option or through Vivado's hardware manager, the error does not occur. This leads me to believe that it is not the Simulink model or reference design that is the issue but either Mathworks' Linux distro or the way the .bit file is loaded onto the SD-card. Also, using the Zedboard's general purpose LEDs directly connected to the XADC-interface, it can be seen that the measurements there are also incorrect, pointing towards the error not being in the communication between PC and Zedboard. Also, every other function works fine; I have tried to run a sine-wave generator on the PL of the board in addition to the XADC and the sine is generated just fine while the XADC provides weird measurements so it is not the entire PL-part of the board producing wrong data but just the XADC.

I have attached a picture of a 10 second scope log (sampled at 100 Hz with 0 voltage input) to this post.

I am using Vivado 2016.4 and MATLAB 2017b as well as the Embedded Coder Linux image on the Zedboard.

So I guess my question is essentially, why does the XADC produce wrong measurements when being loaded from a .bit-file on the Zedboard?

Please let me know if you need any additional information/logs. And thanks for your time

Ps. I do not know whether this is a problem related to the HDL Coder or Vivado (which would make it a Xilinx issue) but due to the error only happening when I use the download option, I guess it has something to do with the way HDL Coder downloads the .bit file to the board.

Answer 1

Hi Frederik,

When you are using the "Download" programming method, the FPGA bitstream is programmed during the Linux boot up process. First the U-boot programs the FPGA bitstream, then it loads the device tree, as well as the Linux kernel.

Xilinx has added the xadc to the Zynq Linux device tree, so once the Linux is boot up, you can access xadc directly from Linux. (https://github.com/mathworks/xilinx-linux/blob/761490a77692f669202fde5e42cdc21cfa263331/arch/arm/boot/dts/zynq-7000.dtsi)

For example, you can try to run >iio_info command in serial console to get the xadc data. There are more details about xadc PS access in this document: https://www.xilinx.com/support/documentation/application_notes/xapp1172_zynq_ps_xadc.pdf

It may be that once Linux boot up, it took control of xadc from the PL. This may be the reason that you cannot get output from xadc any more. And when you are using JTAG, the Linux boot process is not triggered, so Linux does not take control.

I wonder whether it is possible to turn off Linux control using certain command.

Another option may be to take out the devicetree item related to the xadc.

adc: adc@f8007100 {

compatible = "xlnx,zynq-xadc-1.00.a";

reg = 0x20;

interrupts = 7 4;

interrupt-parent = &intc;

clocks = 12;

};

HTH, Wang