MATLAB: Sample time mismatch

Question

after implementing a signal builder instead of single Steps, I get the following message:

"Incoming buses to block 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch' have a sample time mismatch. The signal at input port 1 of 'Thermoschock_aktuell/Rohr/Bus Creator' is of sample time [0, 0], while its corresponding signal at input port 1 of 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Bus Creator' is of sample time [0, 1]. This error message is related to a hidden SubSystem block."

This will happen with some multiport-switches in 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch'. I've currently no idea, why it works with steps, but not with signal builders.

Answer 1

Thanks for the hint. Now it works, after changing sample time of the signal builder block to [0,1] (fixed in minor step).