I am using the Sequence Analyzer (Phasor Type). When I attempt to simulate the model I get the following error:
Output port complex signal mismatch. If all inputs of the Sum block are real signals, then the output of the block must be a real signal. All inputs of block 'test_phasors/Sequence Analyzer (Phasor Type)/Zero Seq. Computation/Sum' are real signals. However, the output port of the block is a complex signal
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