the hdl coder generates real data type which is not synthesizeable, only useful for simulation purpose.
How can we make the hdl coder to generate std_logic_vector before we convert to vhdl
thanks
Best Answer
HDL Coder's bit true and cycle accurate output mirrors precisely what you have placed into your Simulink or MATLAB design. If your design has double or single types, they will be emitted as real in VHDL or Verilog. You will need to convert your modeled types to a non-floating point type, most likely to fixed point. For MATLAB-based designs HDL Coder has fixed-point conversion built into the product workflow. For Simulink-based designs you can use the Fixed-Point Tool to aid you in your conversion.
Please note that opening the Filter Design HDL Coder GUI from the Filter Builder requires the 'Filter Design HDL Coder' toolbox, as mentioned in the following documentation:
The Filter Design HDL Coder can be used to generate synthesizable, portable VHDL and Verilog code for implementing fixed-point filters designed with MATLAB on FPGAs or ASICs.
Best Answer