Hi all! I'm using a Phase Locked Loop block in Simulink (from Matlab R2013b).
When the phase locked loop is locked, the Simulink simulation indicates that the 'locked' signal (at the output of the voltage controlled oscillator) lags the received signal by 270 degrees. I attached my Simulink model (in a zip file) that shows this out-of-phase locking.
Is this supposed to be the usual behaviour of Simulink's phase locked loop block?
I would like to get a Simulink phase locked loop block that will get the VCO output signal and the received signal to be in-phase….. that is, with no phase difference.
Is there another phase locked loop block (or setting) that makes the VCO output become in-phase with the received signal? Thanks all!
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