MATLAB code is untimed code. It has no concept of time, and thus has no need to create or refer to a clocking signal within it. HDL Coder synthesizes a clock, clock enable, and reset when needed. These signals do not appear in the source code. They cannot be referenced by your MATLAB design; if you try to name-match the synthetic signal names, HDL Coder will (as you have seen) modify the name of the synthetic clock signals so that there is no name collision between the user MATLAB and the synthetic clocking signals.
HDL Coder can generate fairly sophisticated clocking patterns, depending on the optimizations and behavioral synthesis options chosen. For example, a large array declaration may infer a RAM. Design permitting, HDL Coder can schedule multiple accesses to this single RAM within a single clock cycle by using a multi-port RAM. Similarly, loops or other repeated structures can be streamed or shared, inferring hardware that runs at multiple rates.
If you have a straightforward design that uses a single clock rate, and you have no need for a clock enable, it can simply be tied high. Newer versions of HDL Coder (you are using the first release to support HDL code generation from MATLAB code) can detect and remove the clock enable in these circumstances.
I recommend taking a look at the examples provided with HDL Coder to understand how state elements are inferred based on your MATLAB code. The clocks themselves are taken care of by the tool.
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