MATLAB: Is the generated HDL code different in Simulink HDL Coder 1.2 (R2007b) when taking the difference of two variables

Question

I am trying to use Simulink HDL coder in a Simulink model to perform simple action on 2 boolean inputs given by:

Out = In1-In2

But instead I see the following line in the generated Verilog code:

assign Add_out1_tmp = (In1 == 1)?In2 - 1 : In2;

This is actually the opposite of what I want to achieve,which is given by

Out = In2-In1

Answer 1

The difference in generated code is not an incorrect behavior in Simulink HDL Coder 1.2 (R2007b).

Since boolean is 1-bit, the operation 'In2-In1' is the same as the operation 'In1-In2' and thus there is no difference in the output.

A workaround would be to use the Logical Operator block in XOR mode. In this case, the code produced looks like:

assign Logical_Operator_out1 =  In1 ^ In2

However this behavior has been changed in Simulink HDL Coder 1.3 (R2008a) to give the output as shown below:

assign Add_out1_tmp = (In1 == 1)? 1 - In2 : -In2