Greetings – I am using a Virtex 5 ML506 board (since my VC707 is not supported) and am trying to do a FPGA in the loop simulation. I have a simple Stateflow diagram that I am trying to compile using HDL Coder. I've set the Target platform to Xilinx Virtex-5 ML506 Development board, the Synthesis tool as Xilinx ISE, etc. When I get to 2.3 in the HDL Workflow Advisor (Check Block Compatibility), it fails saying, "Error: This block is not supported for Xilinx Coregen mapping." This confuses me, as I thought Stateflow was supported. Any advice is welcome here …
MATLAB: Is Stateflow not supported for Xilinx HDL code generation
fpgaHDL CoderHDL Verifierstateflowxilinx
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