MATLAB: Is it possible to use the model slicer in Simulink Design Verifier to generate sliced models based on ‘downstream’ signal propagation

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Is it possible to use the model slicer in Simulink Design Verifier to generate sliced models based on 'downstream' signal propagation? All the examples I've seen only show this in 'upstream', and the 'generate slice' button seems to be disabled when downstream is selected.

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Generating a sliced model with 'Donwstream' or 'Bi-directional' highlighting is not supported. The reason for this is because sliced models are meant to reproduce the original model's simulation behavior. Therefore, if a model is sliced downstream, it eliminates the parts of the model that feed signals to the blocks downstream.

Related Solutions

MATLAB: Does Simulink Design Verifier dead logic analysis depend on model inputs

By default, Simulink Design Verifier will consider the full range of possible input values for only the root-level inports in the model. The possible values for all other model elements are treated as a function of the inports (and global variables). In the case of passing inputs with the "Constant" block, more dead logic will be detected since it will only consider those particular inputs and not the full range.

MATLAB: Sliced variables

To slice the variable 'a', you need to use a subscript list that contains:

One instance of the loop variable
Other subscripts which are either constant literal values or ':'

So, for example, in the following case, 'a' will be a sliced output:

parfor n = 1:35
  tmp = 90 * ones(1, 15);
  a(n, :) = tmp;
end

which creates 'a' as a 35x15 matrix with each element containing the value 90.

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MATLAB: Does Simulink Design Verifier dead logic analysis depend on model inputs

MATLAB: Sliced variables

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