Hi,
I am looking to use the HDL Coder to create verilog from a simulink model but my question is, can this sumlink model be simulated along side the verilog?
I ask as I want to create the overall model of the system using Simulink and then code the system myself in verilog but I want to make sure the verilog I create matches what was expected from the Simulink model.
Thanks, Chris
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