Hello ,
I'm trying to implement a design on Custom board with ATrix-7 series Fpga. I want to generate an IP core which doesn't have any AXI-master/slave or AXI-4 lite interface. Even though I map all the input and output ports to external ports, still the generated IP core contains Enable and reset ports mapped to AXI accessible registers. I tried to custom code it but had no success. Please any one let me know, How I can remove these default AXI_ports (kindly refer the attached picture 1). I this link https://de.mathworks.com/help/hdlcoder/ug/generate-a-custom-ip-core.html, Mathwork reports that one can generate IP core without AXI4 slave interfaces, by clearing the checkbox in the HDL work flow advisor. I'm using Matlab2018_b, I followed all the mentioned steps, but on the last step I dont see an option to uncelar the check box(PS:Fig 2).
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