Hello,
we plan to integrate several HDL coder, system generator and VHDL/Verilog units into one bigger project. I already have experience with implementing such units singly onto one FPGA device but I don't have an idea how to combine them. I am using the Xilinx tool suite (XPS, SDK, ISE).
Has anyone experience with that or knows were to find documentation and/or tutorials for such integration?
A detailed question I have is how I can access resources created in system generator in HDL coder? Is it possible to access registers/specific signals with HDL coder or is the abtraction level too high for that?
Thanks in advance and best regards, Tom
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