Hi,
When simulating the VHDL code generated by Matlab on Vivado, I see that every sample at the input takes 2 cycles of clock like the image below.
The document said that the input sample rate is 30.72 Msps, I understand that 30.72 Msps is the sample rate of ADC and different with clock rate, it makes me a little bit confused about why the sample takes 2 cycles clock here because in the actual case, it takes only 1 cycle clock?
Could you help me with my problem?
Thank you so much!
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