I've been following the example: HW/SW Co-design QPSK Transmitter and Receiver Using Analog Devices AD9361/ AD9364 Hardware Generation Model with the ADI RF SOM – ADRV9361. However once I have finished the process of synthesising and generating the HDL code for the FPGA, I check what's on the board using the following in the command window:
dev = sdrdev('ADI RF SOM') info(dev)
and it returns:
Status: 'Full information' ProtocolVersion: '9.0.0' FirmwareVersion: '9.0.0 for Zynq, build Feb 26 2018 17:19:20' HardwareVersion: '9.0.0 for Zynq, build Aug 14 2018 14:19:29' HardwareRxCapabilities: 'Device does not have targeted Rx DUT' HardwareTxCapabilities: 'Device has targeted Tx: DUT ChannelMapping = 1' RFBoardVersion: 'RF Chip: AD9361, PCORE: version 9.0.98' RFBoardRxCapabilities: 'BasebandSampleRate: [520.9kHz,61.44MHz]; CenterFrequency: [70MHz,6GHz]; NumChannels=2' RFBoardTxCapabilities: 'BasebandSampleRate: [520.9kHz,61.44MHz]; CenterFrequency: [70MHz,6GHz]; NumChannels=2'
Notice only the TX channel has succeeded in arriving on the board – not the Rx – despite the HDL Workflow Advisor claiming successes throughout the process – I cannot figure out why. I've ensured the following:
– Reference Design is set to 'Receive and Transmit path'
– Channel mapping set to 1 (have tried setting to [1 2] and putting Rx and Tx on different channels – no luck)
– All target interface ports are correct
– Generated VHDL definitely includes code for Rx channel as well as Tx
Any advice would be greatly appreciated!
Kind Thanks
Harry
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