MATLAB: How to view the default TCL file for the HDL Workflow Advisor Step 4.3 Build FPGA Bitstream

HDL Coder

How can I view the default TCL file for the HDL Workflow Advisor Step 4.3 Build FPGA Bitstream?

When going through the following example, I can see that there is an option to add a custom "TCL file for synthesis build". I am curious to know what the default TCL file looks like.

https://www.mathworks.com/help/supportpkg/xilinxzynq7000ec/examples/field-oriented-control-of-a-permanent-magnet-synchronous-machine.html

Best Answer

The default TCL file can be found at the following location:

hdl_prj/vivado_ip_prj/vivado_build.tcl

Note that this file only get generated after running Task 4.3 of the HDL Workflow Advisor.

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

As of MATLAB R2019a, HDL Coder only supports one Slave (input) AXI4-Stream interface, and one Master (output) AXI4-Stream interface per IP core. For many SDR and video applications, multiple input or output channels are needed.

At this time, a possible workaround is as follows:

1) In HDL Workflow Advisor Task 1.1, it is necessary to select a specific board for "Target platform" (e.g. "Zedboard"). If you select "Generic Xilinx Platform", it is not currently possible to support this workflow

2) Create and register a custom reference design for the selected board, following the workflow outlined here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/ug/register-a-custom-reference-design.html

To ease this process, you can refer to an existing reference design for the selected board. For example, on a Windows machine the AXI4-Stream reference design for the Zedboard could be found at:

 C:\ProgramData\MATLAB\SupportPackages\R2019a\toolbox\hdlcoder\supportpackages\zynq7000\+ZedBoard\+vivado_stream_2018_2

This will also require exporting a block design from Vivado. A full example of this workflow can be found here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html#d117e22885

3) In the custom reference design file (e.g. "plugin_rd.m"), call the "addAXI4StreamInterface" function multiple times to define multiple AXI4-Stream interfaces. Each one of these can be specified with a different Interface ID to distinguish them. For example, you might do the following in your custom reference design file:

% add first AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_1');
% add second AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm_2/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s_2/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_2');

4) Once this custom reference design is created, you can select it in HDL Workflow Advisor Task 1.2.

5) In HDL Workflow Advisor Task 1.3, you can now select from multiple AXI4-Stream interfaces. Note that due to the current limitations, it will be necessary to model and map the READY signals for all the AXI4-Stream interfaces.

MATLAB: Do I receive the message “No matching files were found” in HDL Workflow Advisor Step 4.2 “Build FPGA Bitstream”

This is a generic error message. Most likely, something went wrong during the build in the synthesis tool (e.g. Xilinx Vivado, Intel Quartus). For example, there might be a licensing error with the synthesis tool, or a critical error occurred during the synthesis or implementation.

To find out more about the underlying issue, check the Vivado/Quartus build logs for errors.

The build logs can be accessed by one of the following methods:

1) Open the project files in the respective synthesis tool IDE and check for error messages. For Vivado, the project files can be found at:

hdl_prj/vivado_ip_prj/vivado_prj.xpr

2) In case you did not select "Run build process externally", the build log can be found at:

hdl_prj/hdlsrc/workflow_task_RunSynthesis.log

Best Answer

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

MATLAB: Do I receive the message “No matching files were found” in HDL Workflow Advisor Step 4.2 “Build FPGA Bitstream”

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