Refer to the example model 'testMdl.mdl' attached to this solution. The model illustrates using both continuous and discretely sampled block such that the SWITCH block has two inputs, namely:
1. Contiuously sampled BUS signals
2. Discrete time feedback signal
In this model the output from the UNIT DELAY block is forced to be continous in time using a Rate Transition block. Further, in the model are used the following blocks:
1. Signal Specification
2. Signal Conversion
Using the Signal Conversion block convert the signal using its copy to a new type (in this case a BUS signal), which is used as a feedback signal to the SWITCH block.
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