MATLAB: How to import the existing Verilog-A code into MATLAB

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Can I import my existing Verilog-A code into some form that can be run from MATLAB.

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This ability to import Verilog-A code is currently not available in MATLAB.

There are no workarounds

Related Solutions

MATLAB: Does converting a multiple port S-parameters to Verilog-A module give me an error

With 55-port input data, the value returned by 'rationalfit' is a 55x55 array of fit objects. As shown in the error message above, the first input argument of 'writeva' must be a scalar, not a 55x55 array.

The solution is to loop through the elements of the fit array by indexing fit(i,j), for example.:

>> status = writeva(fit(1,1),'tmp')
status =
    logical

MATLAB: Can the HDL coder simulate with existing verilog/VHDL codes

Yes, this is possible and easily implemented. If you want to bring existing HDL code into a HDL Coder subsystem, you can do so by using a Subsystem block and setting its HDL Architecture to "BlackBox". (Right click on the Subsystem>HDL Code>HDL Block Properties, choose the BlackBox architecture.)

Once this is done you can configure the control signals that are necessary by using the HDL Block properties dialog. The data input and output ports will be whatever the Subsystem block's interface is; you will need to match the interface of your existing code in Simulink.

For HDL code generation, you don't need anything inside the BlackBox Subsystem. HDL Coder treats it as a black box and expects the associated HDL code to exist separately. If you want to be able to simulate the full design in Simulink or use HDL Coder's testbench or cosimulation capabilities, you will need to provide a matching Simulink behavior inside the black box subsystem.

Another approach from the Simulink simulation perspective is to place your HDL code into your Simulink model with a HDL Verifier cosimulation block inside the BlackBox subsystem. This will let you test your existing code in place via cosimulation, together with the rest of the Simulink model that you are generating code for. This avoids needing to build a parallel subsystem for your existing code.

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Related Solutions

MATLAB: Does converting a multiple port S-parameters to Verilog-A module give me an error

MATLAB: Can the HDL coder simulate with existing verilog/VHDL codes

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