hi, i have a descret PID controller and i want to generate a synthesizable VHDL code to implement on FPGA. i tried to generate a vhdl code which is shown below:
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL;
ENTITY PID IS PORT( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic ); END PID;
ARCHITECTURE rtl OF PID IS
-- SignalsSIGNAL enb : std_logic;SIGNAL out1 : real := 0.0; -- doubleSIGNAL Kd_T_out1 : real := 0.0; -- doubleSIGNAL KiT_out1 : real := 0.0; -- doubleSIGNAL Kp_out1 : real := 0.0; -- doubleSIGNAL Step_out1 : real := 0.0; -- doubleSIGNAL Discrete_output1 : real := 0.0; -- doubleSIGNAL Memory9_out1 : real := 0.0; -- doubleSIGNAL E_k : real := 0.0; -- doubleSIGNAL Product7_out1 : real := 0.0; -- doubleSIGNAL E_k_1 : real := 0.0; -- doubleSIGNAL E_k_E_k_1 : real := 0.0; -- doubleSIGNAL Product6_out1 : real := 0.0; -- doubleSIGNAL Sum3_out1 : real := 0.0; -- doubleSIGNAL E_k_2 : real := 0.0; -- doubleSIGNAL Product8_out1 : real := 0.0; -- doubleSIGNAL Sum2_out1 : real := 0.0; -- doubleSIGNAL Sum8_out1 : real := 0.0; -- doubleSIGNAL Product5_out1 : real := 0.0; -- doubleSIGNAL Sum9_out1 : real := 0.0; -- double
BEGIN out1 <= 2.0000000000000000E+000;
Kd_T_out1 <= 1.0000000000000000E+001;KiT_out1 <= 2.9999999999999999E-001;Kp_out1 <= 1.0000000000000000E+000;E_k <= Step_out1 - Discrete_output1;Product7_out1 <= KiT_out1 * E_k;Memory7_process : PROCESS (clk, reset)BEGIN IF reset = '1' THEN E_k_1 <= 0.0000000000000000E+000; ELSIF clk'event AND clk = '1' THEN IF enb = '1' THEN E_k_1 <= E_k; END IF; END IF; END PROCESS Memory7_process;E_k_E_k_1 <= E_k - E_k_1;Product6_out1 <= Kp_out1 * E_k_E_k_1;Sum3_out1 <= Product7_out1 + Product6_out1;Memory8_process : PROCESS (clk, reset)BEGIN IF reset = '1' THEN E_k_2 <= 0.0000000000000000E+000; ELSIF clk'event AND clk = '1' THEN IF enb = '1' THEN E_k_2 <= E_k_1; END IF; END IF; END PROCESS Memory8_process;Product8_out1 <= E_k_1 * out1;Sum2_out1 <= E_k_2 - Product8_out1;Sum8_out1 <= Sum2_out1 + E_k;Product5_out1 <= Sum8_out1 * Kd_T_out1;Sum9_out1 <= Sum3_out1 + Product5_out1;Discrete_output1 <= Memory9_out1 + Sum9_out1;Memory9_process : PROCESS (clk, reset)BEGIN IF reset = '1' THEN Memory9_out1 <= 0.0000000000000000E+000; ELSIF clk'event AND clk = '1' THEN IF enb = '1' THEN Memory9_out1 <= Discrete_output1; END IF; END IF; END PROCESS Memory9_process;enb <= clk_enable;
END rtl;
the problem is that the generated code cant be compiled in the Quatus. and i see that the problem is in these data:
SIGNAL out1 : real := 0.0; — double SIGNAL Kd_T_out1 : real := 0.0; — double SIGNAL KiT_out1 : real := 0.0; — double SIGNAL Kp_out1 : real := 0.0; — double SIGNAL Step_out1 : real := 0.0; — double SIGNAL Discrete_output1 : real := 0.0; — double SIGNAL Memory9_out1 : real := 0.0; — double SIGNAL E_k : real := 0.0; — double SIGNAL Product7_out1 : real := 0.0; — double SIGNAL E_k_1 : real := 0.0; — double SIGNAL E_k_E_k_1 : real := 0.0; — double SIGNAL Product6_out1 : real := 0.0; — double SIGNAL Sum3_out1 : real := 0.0; — double SIGNAL E_k_2 : real := 0.0; — double SIGNAL Product8_out1 : real := 0.0; — double SIGNAL Sum2_out1 : real := 0.0; — double SIGNAL Sum8_out1 : real := 0.0; — double SIGNAL Product5_out1 : real := 0.0; — double SIGNAL Sum9_out1 : real := 0.0; — double in which they must be std_logic and not real. so i didnt find which parameters can be set in matlab? thank you very much
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