Simscape Hardware-in-the-Loop Workflow
Automatic replacement of Simscape subsystem with state-space implementation
In R2020b, the Simscape HDL Workflow Advisor automatically replaces the Simscape™ subsystem with the state-space implementation in the HDL implementation model. You do not have to modify the HDL implementation model, and can directly generate HDL code for the model and then deploy the code onto Speedgoat FPGA I/O modules.
In addition, when you select the Generate validation logic for the implementation model check box, the Advisor generates the HDL implementation model and a state-space validation model.
Automatic setting of number of solver iterations in Simscape HDL Workflow Advisor
Previously, when you ran the Simscape HDL Workflow Advisor, in the Generate implementation model task, the Number of solver iterations was specified as 5 for switched linear models. When you generated the HDL implementation model, in some cases, you had to iterate multiple times to get the optimal number of solver iterations.
In R2020b, depending on your Simscape model, the Advisor automatically determines an optimal number of solver iterations that causes the model simulation to converge and avoids exceeding the threshold value for real-time deployment.
Mapping of state-space parameters to RAM in HDL implementation model
For large Simscape models, the generated HDL implementation model can have large state-space parameters. These state-space parameter matrices consumed a large number of FPGA lookup table resources on the FPGA, and might cause the design to not fit on the target FPGA device.
To save lookup table resources, you can now map the state-space parameter matrices to Block RAM resources on the FPGA. In the Generate implementation model task, the Map state space parameters to RAMs setting is specified as Auto, which maps state-space parameters to RAMs.
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