MATLAB: How to Configure “use ieee.std_logic_unsigned.all; ” in HDL Coder

HDL CoderMATLABsimulinkuse ieee.std_logic_unsigned.all;vhdl

Is it possible to configure HDL Coder to generate VHDL code using "use ieee.std_logic_unsigned.all; " package ?

Best Answer

The use of std_logic_unsigned, while convenient, is not supported by HDL Coder. Many people in the industry feel the use of the std_logic_unsigned and std_logic_signed packages can lead to a lack of clarity in VHDL code. The explicit use of the signed, unsigned, and std_logic types is a code style that leads to an unambiguous definition of each signal's type and an indication of what operations are permitted. This style is what is supported by HDL Coder.

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MATLAB: How to “use structures for function arguments”

Try this

S.x1     = 17   ;
S.x2     = 18   ;
S.text1  = 'ABC';
S.cmap1  = magic(3);
S.cmap2  = magic(3);
S.cmap3  = magic(3);
S.cmapA  = magic(3);
S.cmapH  = magic(3);
S.text2  = 'DEF';
S.x3     = 19   ;
S.x4     = 20   ;
S.x5     = 21   ;
%

[y1,y2] = myfun( S );
%
function [y1,y2] = myfun( S )
    if not( isfield( S, 'cmapB' ) )
        S.cmapB = rand(3); % default value
    end
    y1 = S.x1;
    y2 = S.x2;
end

MATLAB: Does HDL Coder support the VHDL fixed-point and floating-point packages

No. To ensure full portability and numerical consistency with MATLAB rounding and saturation, HDL Coder generates this functionality using the IEEE std_logic_1164 and numeric_std packages. Since operations with different fixed-point data types are properly handled within MATLAB and Simulink, and the generated HDL matches the original MATLAB/Simulink model, there’s no real need to use fixed-point packages in the VHDL.

To help with readability, HDL Coder generates comments with the corresponding MATLAB types, for example:

SIGNAL data_in_signed : signed(17 DOWNTO 0); -- sfix18_En11

SIGNAL Constant_out1 : signed(17 DOWNTO 0); -- sfix18_En11

SIGNAL Tapped_Delay_out1 : vector_of_signed18(0 TO 10); -- sfix18_En11 [11]

SIGNAL Tapped_Delay_out1_1 : vector_of_std_logic_vector18(0 TO 10); -- ufix18 [11]

SIGNAL MidSample : std_logic_vector(17 DOWNTO 0); -- ufix18

Best Answer

Related Solutions

MATLAB: How to “use structures for function arguments”

MATLAB: Does HDL Coder support the VHDL fixed-point and floating-point packages

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